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| (R) STLC3080 SUBSCRIBER LINE INTERFACE CIRCUIT PRELIMINARY DATA MONOCHIP SLIC SUITABLE FOR PUBLIC APPLICATIONS IMPLEMENTES ALL KEY FEATURES OF THE BORSHT FUNCTION DUAL CONTROL MODE CONFIGURATION: SLAVE MODE OR AUTOMATIC ACTIVATION MODE. SOFT BATTERY REVERSAL WITH PROGRAMMABLE TRANSITION TIME ON HOOK TRANSMISSION LOOP START/GROUND START FEATURE WITH PROGR. THRESHOLD LOW POWER DISSIPATION IN ALL OPERATING MODES AUTOMATIC DUAL BATTERY OPERATION INTEGRATED RING TRIP DETECTION WITH AUTOMATIC AND SYNCRONISED RING DISCONNECTION METERING PULSE INJECTION SURFACE MOUNT PACKAGE THREE RELAY DRIVERS FOR RING AND TESTING BLOCK DIAGRAM REL0 REL1 RELR RGND TQFP44 (10 x 10) ORDERING NUMBER: STLC3080 -40 TO +85C OPERATING RANGE DESCRIPTION The STLC3080 is a SLIC device suitable for a wide range of applications: public (CO), transmission (DLC) and private (PABX). The SLIC provides the standard battery feeding with full programmability of the DC characteristic. In particular two external resistors allow to set the limiting current value (up to 50mA) and the value of the resistive feeding when not in constant current region. CRT RT1 RT2 PCD MODE D0 D1 D2 R0 R1 DET GDK/AL CSIN CSOUT CKRING RES TTXIN ZB TX RX AC PROCESSOR LOGIC INTERFACE & DECODER LINE STATUS ILT SUPERVISION COMMANDS ILL LINE INTERFACE TIP RING AC+ DC AC DC BGND VREG + ILTF REFERENCE & BIAS SWITCHING DC PROCESSOR RLIM RTH ZAC1 ZAC RS CAC IREF VCC VDD AGND CREV CSVR VBAT BASE RDC D98TL305B December 1999 This is preliminary information on a new product now in development or undergoing evaluation. 1/23 STLC3080 PIN CONNECTION CKRING GDK/AL MODE BGND VREG 44 43 42 41 40 39 38 37 36 35 34 CSOUT CSIN D0 D1 D2 R0 R1 RES VDD VCC CRT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RS RGND RELR VBAT ZAC1 REL1 REL0 ZAC RX TX ZB D98TL306A BASE RING PCD DET TIP CSVR 33 32 31 30 29 28 27 26 25 24 23 CREV IREF RLIM RTH AGND RT1 RT2 ILTF RDC CAC TTXIN ABSOLUTE MAXIMUM RATINGS Symbol VBAT VCC VDD IREL A/R/BGND Battery voltage Positive supply voltage Control Interface Supply Voltage Current into relay drivers AGND respect BGND respect RGND Parameter Value -80 + VCC to +0.4 -80 + VREL to + 0.4 -0.4 to +7 -0.4 to +7 80 -2 to +2 Unit V V V V mA V OPERATING RANGE Symbol TopT VCC VDD VBAT A/R/BGND PD (70) PD(85) Positive supply voltage Control Interface Supply Voltage Battery voltage if VREL > VCC AGND respect BGND respect RGND Max. power dissipation @ Tamb = 70C Max. power dissipation @ Tamb = 85C Parameter Operating temperature range Value -40 to +85 4.75 to 5.25 3 to 5.25 -73 to -15 -78 + VREL to -15 -0.3 to +0.3 1.1 0.9 Unit C V V V V V W W THERMAL DATA Symbol Rth j-amb 2/23 Parameter Thermal resistance Junction to Ambient Typ. Value 60 Unit C/W STLC3080 PIN DESCRIPTION Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name CSOUT CSIN D0 D1 D2 R0 R1 RES VDD VCC CRT REL1 REL0 RELR RGND VBAT TX ZB RS ZAC ZAC1 RX TTXIN CAC RDC ILTF RT2 RT1 AGND RTH RLIM IREF CREV CSVR BASE VREG BGND RING TIP PCD MODE CKRING DET GDK/ AL Description Chip-Select for output control bits DET and GDK . Active Low. (*) Chip-Select for input control bits latches D0 D1 D2 R0 R1 . Active Low. (*) Control Interface input bit 0. (*) Control Interface input bit 1. (*) Control Interface input bit 2. (*) Relay driver 0 command. Active High. (*) Relay driver 1 command. Active High. (*) Reset Input; active low. Control interface Power Supply. VDD = 3.3V or V DD = VCC. Positive Power Supply (+5V). Ring-Trip time constant capacitor. Relay 1 driver output. Relay 0 driver output. Ringer Relay driver output. Relay drivers ground. Negative Battery Supply. 4 wires output stage (Transmitting Port). Cancelling input of Balance Network for 2 to 4 wires conversion. Protection resistors image. The image resistor is connected between this node and ZAC. AC impedance synthesis. RX buffer output/ AC impedance is connected between this node and ZAC. 4 wires input stage (Receiving Port). A 100K external resistor must be connected to AGND to bias the input stage. Metering Signal Input (AC) and Line Voltage Drop Programming (DC). If not used must be connectd to AGND. AC feedback input/ AC-DC split capacitor is connected between this node and ILTF. DC current feedback input. The RDC resistor is connected between this node and ILTF. Transversal Line Current Image. Input pin to sense ringing current , for Ring-Trip detection. Input pin to sense ringing current , for Ring-Trip detection. Analog ground. Off-Hook threshold programming pin. Limiting current programming pin. Voltage reference output to generate internal reference current. Reverse polarity transition time programming. Battery supply filter capacitor. Driver of the external transistor. Connected to the base. Regulated voltage. Provides the negative supply to the power line drivers. It is connected to the emitter of the external transistor. Battery ground. B wire termination output. IB is the current sunk into this pin. A wire termination output. IA is the current sourced from this pin. Power Cross Detection Input Interface Control Mode selection. Clock at ringing frequency for relay synch and time reference for Automatic activation Off-hook and Ring-Trip detection bit. Tri-State Output/Active Low. Ground-Key/Alarm detection bit. Tri-State Output. Active Low. * Input pins provided with 15A sink to AGND pull-down. 3/23 STLC3080 CONTROL INTERFACE Slave mode (MODE=Low). INPUTS R0 X X X X X X X X 0/1 X R1 X X X X X X X X X 0/1 D0 0 0 0 0 1 1 1 1 X X D1 0 0 1 1 0 0 1 1 X X D2 0 1 0 1 0 1 0 1 X X OPERATING MODE Power down Stand-by Active N.P. Active R.P. Ringing (with SLIC Active N.P.) Ringing (with SLIC Active R.P.) Ground start High Impedance Feeding Rel 0 (on = 1, off = 0) Rel 1 (on = 1, off = 0) OUTPUTS DET GDK/AL (Active Low) (Active Low) disable disable gnd-key off/hk gnd-key off/hk gnd-key off/hk disable ring/trip disable ring/trip gnd-key off/hk disable off/hk def by D0-D2 def by D0-D2 def by D0-D2 def by D0-D2 A parallel interface allow to control the operation of STLC3080 through a control bus: - D0 D1 D2 latched input bits defining the Slic operation mode - R0 R1 latched input bits (active High) drive the test relays. - DET and GDK/AL , tri-state outputs, signal the status of the loop: On/Off-Hook and Ground-Key. Pin GDK/AL goes low also when the device thermal protection is activated or a line fault (Tip to Ring, Tip and/or Ring to Ground or VBAT) is detected(flowing current 7.5mA). -CSIN: chip select for input bits, active Low, strobes the data present on the control bus into the internal latch. - CSOUT: chip select for output bits ; active Low , when high DET and GDK/AL goes tri-state. D0 D1 D2 R0 R1 CSIN and CSOUT inputs are provided with a 15A pull-down current to prevent uncontrolled conditions in case the control bus goes floating. According to the above table, 8 operating modes can be set: 1) Power-Down. 2) Stand-By. 3) Active N.P. 4) Active R.P. 5) Ringing (with SLIC Active N.P.). 6) Ringing (with SLIC Active R.P.). 7) Ground start. 8) High Impedance Feeding. Power-Down It's an idle state characterised by a very low power consumption; any functionality is disabled; only relays Rel0 and Rel1 can be driven by proper setting of bits R0 and R1. It can be set during out of service periods just to 4/23 reduce the power consumption. It is worth noticing that two other conditions can set the Slic in idle state but with some differences as reported in the table: Idle State Power Down Reset Thermal Alarm Rel0/1 Drive Enable Disable Enable DET Disable Disable Low GDK/AL Disable Disable Low Stand-By. Mode selected in On-Hook condition when high immunity to common mode currents is needed for the DET bit. To reduce the current consumption, AC feedback loop is disabled and only DET and GDK/AL detectors are active. DC current is limited at 16mA (not programmable); feeding characteristic shown in fig. a. The voltage drop in on-hook condition is 7.8V. Figure a: STLC3080 DC Characteristic in Stand-By Mode. I 16mA RFEED = 2RP D98TL307 VBAT -7.8V V Active Mode selected to allow voice signal transmission. When in ACTIVE mode the voltage drop in onhook condition is 7.8V in order to allow proper onhook transmission (Fig. b). STLC3080 Figure b. STLC3080 DC Characteristic in Active Mode. I ILIM [20/50mA] RFEED = RDC 5 +2RP RFEED = 2RP VBAT -7.8V VBAT V Ground Start. This mode is selected when the SLIC is adopted in a system using the Ground Start feature. In this mode the TIP termination is set in High Impedance (100k) while the RING one is active and fixed at Vbat +4.8V. In the case of connection of RING termination to GND the sinked current is limited to 30mA. When RING is connected to GND both Off-Hook and Ground-Key detectors become active. Power dissipation in this mode with a -48V battery voltage is 100mW Resistive Region is programmable by means of external resistor RDC, limiting current can be selected by RLIM resistor. Concerning AC characteristic the STLC3080 allows to set 2W termination impedance by means of one external scaled impedance that may be complex. Two to four wire conversion is provided by an external network. Such network can be avoided in case of application with COMBOII, in this case the two to four wire conversion is implemented inside the COMBOII by means of the programmable Hybal filter. When in ACTIVE mode it is also possible to perform battery reversal in soft mode (with programmable transition time) without affecting the AC signal transmission. Ringing When Ringing mode is selected the STLC3080 activates the ring relay injecting the ringing signal on the line. As the ring trip is detected the logic indicator DET is set low and the ringing is automatically disconnected without waiting for the card controller command (auto ring trip). DET remains latched Low untill the operative mode is modified. If required , the ringing relay drive signal RELR can be synchronised to a clock applied to CKRING input. This clock is derived from the ringing signal with proper time delay, according to the activation/deactivation time of the relay. RELR is activated on the low level of CKRING clock. The duty cycle of CKRING can be modified in order to activate the RELR when required: CKRING low must last 1s minimum. If the synchronisation is not required, CKRING input must be steadily kept Low. All the STLC3080 relay drivers are open drain with the source connected to the RGND pin. Each relay drivers integrates a protection structure that allows to avoid external kick - back diodes, using both 5V or 12V relays. The ring trip circuit and its behaviour is described in Appendix D. High Impedance Feeding. As Stand-By, this mode is set in On-Hook condition, with further reduced power consumption. Higher power efficiency turns back a lower immunity of the Off-Hook detector to line common mode currents. The DC feeding shows a constant current characteristic (Ilim = 17mA) followed by a resistive range with an equivalent series resistance RFEED = 1600 + 2Rp. Thermal protection circuit is still active, preventing the junction temperature, in case of fault condition, to exceed 150C In High Impedance Feeding most of the circuit is switched off, only the circuit, dedicated to OffHook detection, is powered. This allows to reduce the total power consumption in On-hook to 30mW (typical). The Off-Hook detection threshold is not programmable but defined at a fixed IDETHI = 8mA(max.) Figure c. STLC3080 DC Characteristic in High Impedance Feeding I 17mA RFEED = 1600 +2RP D98TL373 VBAT -0.8V V 5/23 STLC3080 CONTROL INTERFACE Automatic activation mode (MODE=High). R0 X X X X X X X X 0/1 X X R1 X X X X X X X X X 0/1 X Inpu ts D0 D1 0 0 0 0 0 1 0 1 1 1 1 X X X 1 0 0 1 1 X X X D2 0 1 0 1 0 1 0 1 X X X RES 1 1 1 1 1 1 1 1 1 1 0 Operating Mode (Mode = High) Power Down Ringing On-Hook Transmission Reverse Polarity On-Hook Transmission Direct Polarity Active Direct Polarity (default) Active Direct Polarity (default) Active Reverse Polarity Active Direct Polarity (default) R0 = 0/1: Rel0 = off/on R1 = 0/1: Rel1 = off/on Power Down; Rel0/1 = off Outputs DET GDK/AL disable disable Ring-Trip disable Off-Hook Fault Fault Off_Hook Fault Fault Off_Hook Fault Fault Off_Hook Fault Fault Off_Hook Fault Fault Off_Hook Fault Fault (1) (1) (1) (1) disable disable DET: On/Off Hook Signalling ; together with GDK/AL it is set Low also in case of Thermal Alarm or Ground-Key. GDK/AL : Thermal Alarm or Ground-Key Signalling (1) : DET and GDK/AL signalling function is related to D0,D1,D2 and it doesn't depend on R0 and R1 setting. As in Slave mode the control is performed through a parallel bus, with independent chip selects, CSIN and CSOUT, for inputs and outputs. In Automatic Activation, once Active mode is selected the device automatically selects the proper operating mode (Active, Stand By or H.I. feeding) depending on the loop status in order to optimise the power consumption. In order to guarantee the proper behaviour of the internal state machine the "CKRING" signal must be always applied, this signal in fact is used to generate the "WTIME" delay (see Appendix) necessary to properlyperform automatic state change. Power-Down It's an idle state characterised by a very low power consumption; any functionality is disabled; only relays Rel0 and Rel1 can be driven by proper setting of bits R0 and R1. It can be set during out of service periods just to reduce the power consumption. It is worth noticing that two other conditions can set the Slic in idle state but with some differences as reported in the table: Idle State Rel0/1 Drive Power Down Enable Reset Disable Thermal Enable Alarm DET Disable Disable Low GDK/AL Disable Disable Low As a Ring-Trip is detected the logic indicator DET is set Low and the ringing relay is automatically switched-off without waiting for the card controller command (auto ring-trip). DET remains latched Low until the operative mode is modified. Ringing relay drive signal RELR must be synchronised to a clock applied to CKRING input. This clock is derived from the ringing signal with proper time delay, according to the activation / deactivation time of the relay. RELR is activated on the low level of CKRING clock. The duty cycle of CKRING can be modified in order to activate the RELR when required: CKRING low must last 1s minimum. All the relay drivers are open-drain with the source connected to RGND pin. Each relay driver integrates a protection structure to avoid external kick-back diodes using both 5V or 12V relays. The ring trip circuit and its behaviour is described in Appendix D. On-Hook Transmission. Sets the Slic for conversation even though the line is in On-Hook; it is required for On/Hook transmission purposes; Active mode cannot support a conversation when the line is in On-Hook as it automatically turns in High Impedance Feeding. Active. The relevant feature of this setting is that when Active Mode (D0D1D2=1XX) is set by the external control , internally, the device is able to select between three operative states according to the status of the line: Ringing When Ringing mode is selected the STLC3080 activates the ringing relay injecting the ringing signal on the line. 6/23 STLC3080 - High Impedance Feeding : entered after a Power-On Reset or 1XX word, this status is set during steady On/Hook condition; most of the circuitry is idle and only a low power Off-Hook detection circuit is kept alive. Direct Polarity only is assumed , independently of the selected one. To minimise the power consumption the Off-Hook detectioncircuit has low common mode current rejection. - Standby Notice that in Stand-By state the Off-Hook detector is sensitive only to the transversal component of the line current with high immunity to common mode disturbances; this performance implies an increasing in power consumption: for that reason Stand-By is not used as a quiescent state. - Active state gets operative for conversation after an Off-Hook validity check performed in Stand-By state, set after any Off-Hook detected in High Impedance Feeding. If the Off-Hook condition is confirmed in Stand By, Active mode is set ; if not (in case of spurious detection), false activation is prevented, and High Impedance Feeding is resumed. In order to have the device falling back in HI-feeding mode after the line is back in on-hook condition. It is necessary to select as input state the active direct polarity mode (default). During Active state On/Off-Hook status will affect in real time DET signalling bit. In order to allow Pulse-Mode Dialling, once Active state is set, it cannot be changed by fast OnHook , but it is turned back to High Impedance Feeding only if an On-Hook condition lasts longer than 128 x CKRING period. Automatic activation (and deactivation) is based on an internal state-machine which is clocked by a free running internal oscillator. A detailed description is reported in the AppendixA. DUAL BATTERY CONFIGURATION STLC3080 is also meant for low power consumption systems using Dual Battery solution. It is sufficient to connect the collector of the external transistor, through a diode, to the reduced battery (see Fig. 2 for single battery solution and Fig. 3 for dual battery solution). The activation of the batteries is automatic, only depending on the DC load at the RING and TIP terminals; no controllers action is required. PROTECTION CIRCUIT - Suggested protection circuit is based on programmable Trisils (like LCP1511/2) as shown in Fig.2 and Fig. 3, and the surge current is limited by the resistors RPT2 and RPR2, which are PTC types , protecting the device against both lightning and power-cross. - Additionally, STLC3080 is provided with the PCD input to directly monitor overvoltages applied to the line wires. When the current injected into PCD exceeds a threshold of 320A (+/- 30%) , DET and GDK/AL are set Low signalling a fault condition. No change on the SLIC mode is performed. Voltage threshold is defined by proper value of the series resistors (see Fig.1) This circuit gives the possibility to protect the device against power crosses through a relay instead of PTCs; once the fault condition is detected the controller drives this relay disconnecting the Slic from the line terminals. METERING PULSE INJECTION Figure 1. VCC DET R TIP R RING Ith CSOUT PCD GDK/AL D98TL385 STLC3080 provides external pins and components for Metering Pulse injection. TTXIN pin is the input for the 12kHz or 16kHz Metering Pulse injection. This pin also provides a DC constant current source that is injected into the external RDA resistor (typ. 10k to obtain 2.2Vrms on 200) connected between TTXIN pin and AGND. The voltage drop across TIP and RING line amplifiers and, consequentallythe AC swing available. When Metering Pulse injection is not used and voltage drop is not required, TTXIN must be shorted to AGND and RTTX, RDA and CTTX external components must be removed. The TTX cancellation is obtained through an external RTTX and CTTX network connected between TTXIN and CAC pins. Fault detection The device provides current sense on TIP and RING wires that allow to detect longitudinal DC current (ILL). When this ILL current becomes higher than a threshold (see detectors table inside electrical characteristics) a fault indication is provided on DET and GDK pin (both outputs become low). The fault indication is active till the fault cause persists. With this circuit the following fault condition can be detected. TIP to VB1 TIP to GND RING to VB1 RING to GND RING to TIP to VB1 7/23 STLC3080 When a fault is detected the line current is limited in order to avoid any damage on the device itself and also on the external transistor. MISCELLANEOUS - Thermal overload: the integrated thermal protection is activated when Tj reaches 150C typ.; the Slic is forced in Power-down mode, DET and AL are set Low. The RELR relay driver is turned off while it is still possible to control REL0 and REL1 through R0 and R1 inputs. - One low cost external transistor allows to reduce the power dissipated in the SLIC itself allowing the use of extreme small size package (TQFP44). The external transistor size/package can be selected depending on the max. power requested by the particular application. - The SLIC supports loop start lines and gives the possibility to set loop current indicator threshold by means of one external resistor. EXTERNAL COMPONENTS LIST To set the SLIC into operation the following parameters have to be defined: - The DC feeding resistance "Rfeed" defined as the resistance of the traditional feeding system (most common Rfeed values are: 400, 800, 1000 ohm). - The AC SLIC impedance at line terminals "Zs" to which the return loss measurements is referred. It can be real (typ. 600 ohm) or complex. - The equivalent AC impedance of the line "Zl" used for evaluation of the trans-hybrid loss performance (2/4wire conversion). It can be a complex impedance. - The value of the two protection resistors Rp in series with the line termination. - The reverse polarity transition time defined as "VTR/T". - The constant current limit value "I lim". - Rth: sets the OFF/Hook DETection threshold Once, the above parameters are defined, it is possible to calculate all the external components using the following table. EXTERNAL COMPONENTS Name CVCC CVB R REF (*) CSVR CRT R DC C AC RS ZAC ZA ZB C COMP RR RS1 RS2 RT QEXT RPT1 RPR1 Function Positive Supply Filter Battery Supply Filter Internal current reference programming resistor Battery ripple rejection capacitance Ring Trip capacitance DC sinthesized resistance programming resistor AC/DC splitter capacitance Protection resistor image 2 wire AC impedance SLIC impedance balancing network Line impedance balancing network AC feedback compensation capacitance Feeding resistance for Ring Injection Sensing resistor for Ring Trip Sensing resistor for Ring Trip Feeding resistance for Ring Injection External transistor Line series resistor Line series resistor 1.16 IREF = RREF CSVR = 1 2 fp 1.3M Formula Typical Value 100nF 20% 100nF 20% 100V 30.1k 1% 100nF 10% 100V @ fp = 1.22Hz 470nF 20% 6V @ 25Hz 1.5k 1% 10F 20% 15V @ fsp = 10Hz 2.5k 1% 12.5k 1% 15k 1% 15k 1% 220pF 20% @ fo = 250kHz 600 2W 600k 1% 600k 1% 0 BD140 20 1/4W 1% see Appendix D R DC = 5[Rfeed -2Rp] R DC 1k CAC = 1 2 fsp RDC R S = 25 2Rp Z AC = 25[Zs - 2Rp] ZA = 25 Zs ZB = 25 Zl 2 CCOMP = 2 fo[100 Rp] 400 1000 RR 1000 RR 0 (1) 20 20 8/23 STLC3080 EXTERNAL COMPONENTS (continued) Name RLIM (*) Function Current limiting setting resistor Formula 1.16 RLIM = 103 ILIM 23.2k / 58k 1.16 ITH 21.1k / 77.3k RTH = 200 CREV = 1 K ; K= 3750 VTR T Drop 20k 9.6 - Drop Typical Value 51.1k 1% RTH (**) OFF/HOOK DETection threshold setting resistor. 26.1k 1% CREV Polarity reversal transition time programming 47nF for 5.67V/ms RDA R1, R2 RTTX CTTX OutputVoltageDropAdjustment Power Cross Detection Teletax Cancellation Resistor Teletax Cancellation Capacitor RDA = 10k (Drop = 3.2V) (2) 240k (3) R TTX = 12.5 [Re (ZLTTX) + 2RP] CTTX = 8 8 1 3.75k 20 1/4W 1% (12.5 Im (ZLTTX) 2 fTTX) RPT2 RPR2 D1 D2 CH Protection resistor Protection resistor Overvoltage protection Dual Battery Operation Trans-Hybrid Loss Frequency Compensation 1N4448 1N4448 CH = CCOMP 220pF 30% Notes: (1) Transistor characteristics: hFE 25, IC 100mA, VCEO 60V, fT 15MHz. PDISS depends on application, see Appendix. For SMD application possible alternatives are MJD350 in D-PACK or BCP53 in SOT223 (2) Typical value needed for 2.2Vrms metering pulse level, if no metering RDA = 0. (3) These resistors are needed to activate the power cross detection circuit, they should withstand the typical lighting voltage. If the power cross detection is not needed R1, R2 can be avoided. (*) RREF and RLIM should be connected close to the corresponding pins of STLC3080. Avoid any digital line or high voltage swing line to pass close to IREF and RLIM pins. Eventually screen these pins with a GND track. (**) Inside the formula the coefficient 1.16 must be changed to 1.20 if the selected value of Ith is lower than 5mA. 9/23 STLC3080 Figure 2. Typical application diagram. CVCC VCC VDD VREL ZAC1 ZAC RS RX TX ZAC RS ZA CCOMP RX TX ZB ZB CH MODE D0 D1 D2 R0 CONTROL INTERFACE R1 DET GDK/AL CSIN CSOUT RES CKRING TTX VCC VDD AGND BGND RGND REL0 REL1 RELR PCD RPT1 TIP LCP 1511 RPR2 LB RT R2(1) RPT2 LA R1(1) VBRPR1 MODE D0 D1 D2 R0 R1 DET GDK/AL CSIN CSOUT RES CKRING TTXIN CAC ILTF RDC RDC + CTTX CAC CRT IREF RLIM RLIM RTH RING STLC3080 RT1 RS1 RS2 RT2 QEXT VREG BASE VBAT CVB D1 RR VRING VB- CSVR CREV VB- (2) RDA RTTX D98TL308C CRT RREF RTH CREV CSVR (1) This components are needed only for Power Cross Indication (normally not used). (2) Components needed only for Metering pulse injection. Figure 3. Typical dual battery application diagram. CVCC VCC VDD VREL ZAC1 ZAC ZA CCOMP RS RX TX ZAC RS RX TX ZB CH ZB MODE D0 D1 D2 CONTROL INTERFACE R0 R1 DET GDK/AL CSIN CSOUT RES CKRING TTX VCC VDD AGND BGND RGND REL0 REL1 RELR RT PCD RPT1 TIP LCP 1511 RPR2 LB RPT2 LA R2(1) R1(1) VBRPR1 MODE D0 D1 D2 R0 R1 DET GDK/AL CSIN CSOUT RES CKRING TTXIN CAC ILTF RDC RDC + CTTX CAC CRT IREF RLIM RLIM RING STLC3080 RT1 RS1 RS2 RT2 QEXT VREG BASE VBAT CVB CSVR CREV RTH RTH VB2 D1 VBD2 VBRR VRING (2) RDA RTTX CRT RREF CREV CSVR D98TL310C (1) This components are needed only for Power Cross Indication (normally not used). (2) Components needed only for Metering pulse injection. 10/23 STLC3080 ELECTRICAL CHARACTERISTICS (Test Condition, unless otherwise specified: VCC = 5V, VDD = 3.3V, VB- = -48V, AGND = BGND = RGND, Tamb = 25C). Note: the limits below listed are guaranteed with the specified test condition and in the 0 to 70C temperature range. Performances over -40 to +85C range are guaranteed by product characterisation. Symbol Parameter AC CHARACTERISTICS Zil Long. Impedance Iil Long. Current Capability AC Test Condition each wire H.I. feeding per wire (ONHOOK) STANDBY or ACTIVE per wire (ON-HOOK) ACTIVE per wire (OFFHOOK). IT = Transversal Current NP with nominal RP at 300Hz NP with nominal R P at 1020Hz NP with nominal R P at 3040Hz NP with nominal RP at 300Hz NP with nominal R P at 1020Hz NP with nominal R P at 3040Hz 300 to 3400Hz 1020Hz; 20Log |VRX/VTX| ACTIVE MODE at line terminals on ref. imped. 0dBm 1020Hz 0dBm 1020Hz rel. 1020Hz, 0dBm 300 to 3400Hz rel. 1020Hz, 0dBm 300 to 3400Hz f = 10120Hz, input level from 3dBm to -40dBm psophometric, Active On Hook psophometric, Active On Hook 0dBm, 1KHz Il = 20 to 45mA VTTX = 100mVRMS @ 16kHz Min. Typ. Max. 40 5 13 80 -IT Unit mApk mApk mApk Fig. L/T Long. to transv. T/L Transv. to long 2wRL THL Ovl TXoff G24 G42 G24fq G42fq G24lv G42lv V2wp V4wp Thd GTTX 2W return loss. trans-hybrid loss. 2W overload level TX output offset Transmit gain abs. Receive gain abs. tx gain variation vs. frequency rx gain variation vs. frequency Tx gain variation vs. level Rx gain variation vs. level idle channel noise at line terminals idle channel noise at TX port total harm. dist. 2w-4w, 4w2w Transfer Gain 60 60 55 37 40 40 22 30 3.2 -200 -12.38 5.74 -0.1 -0.1 -0.1 -0.1 -82 -90 200 -12.02 6.1 0.1 0.1 0.1 0.1 -78 -84 -50 14.5 dB dB dB dB dB dB dB dB dBm mV dB dB dB dB dB dB dBmp dBmp dB dB C5 C6 C2 C4 C1 C8 C7 VL GTTX = 20Log VTTX with RL = 200 THD (TTX) TTX Harmonic Distortion 2.2V RMS = on 200 DC CHARACTERISTICS (TTX pin connected to ground) Vlohi Line voltage Il = 0, H.I. feeding Vlo Line voltage Il = 0, SBY/ACTIVE/ONHOOK Ilims Short circ. curr. Rloop = 0, SBY Ilimb Short circ. curr. Rloop = 0, H.I. feeding Ilima Lim. current accuracy Rel to progr. val. 20 to 50mA ACTIVE NP, RP VIREF Bang up reference Rfeed Feed res. accuracy ACTIVE NP, RP Rfeed H.I. Feeding resistance H.I. feeding 3 47 38.9 14 11 -10 1.08 -10 1100 47.4 39.9 16 17 47.8 40.9 18 20 10 1.24 10 2100 % V V mA mA % V % 11/23 1.16 STLC3080 ELECTRICAL CHARACTERISTICS (continued) Symbol Ilact Ilsby ITIP IGS IDA Parameter Feed current ACTIVE Feed current STBY Test Condition ACTIVE NP, RP Rloop = 1900 RDC = 1.5k STY, Rloop = 2.2K RDC = 1.5k Ground Start Ground Start Ring to GND VTTX = 0V Min. 18 13 1 -70 33 -60 -45 Typ. 20 Max. Unit mA mA A mA A Fig. Tip leackage current Ring Lead Current Reference current sourced by TTX IN pin for Voltage Drop programming DETECTORS Idet Off-hook current threshold ST-BY, ACTIVE Idet H.I. Hys Td ILL Off-Hook current threshold Off/On hook hyst. Dialling distortion Ground Key Current threshold ILL = IB - IA Igst Ground Start detection Igst = 2 Idet threshold GROUND START DIGITAL INTERFACE INPUTS: D0, D1, D2, R0, R1, CSIN, CSOUT Vih Input high voltage VDD = 3.3V Vil Input low voltage VDD = 3.3V Iih Input high current Iil Input low current OUTPUTS: DET, GDK /AL Vol Output low voltage Iol = 0.5mA; CSOUT = LOW Voh Output high voltage Ioh = 0.1mA; CSOUT = LOW IOZ Tri-State Output Current CSOUT = High OUTPUTS: RELR, REL0, REL1 Ird Current capability Vr Output voltage Ird = 40mA Ird = 70mA Iik Off leakage current POWER SUPPLY REJECTION PSRRC VCC to 2W port Vripple = 0.1Vrms 50 to 4000Hz PSRRB Vbat to 2W port Vripple = 0.1Vrms 50 to 4000Hz POWER CONSUMPTION VCC supply current H. I. Feeding On-Hook ICC From 0 to 70C From -40 to 85C SBY On-Hook From 0 to 70C From -40 to 85C Active On-Hook From 0 to 70C From -40 to 85C Power Down From 0 to 70C From -40 to 85C 12/23 Rel. to progr. val. 7 to 11mA Rel. to progr. val. 3 to 6mA H.I. feeding ST-BY, ACTIVE ACTIVE TIP to RING to GND or RING to GND -10 -20 5 15% Idet -1 7.5 +10 +20 8 +1 % % mA mA ms mA -10 +10 % 2 0.8 30 10 0.45 2.4 -10 40 0.6 1.1 3 27 30 +10 V V A A V V A mA V V A dB dB C9 C9 1.0 1.5 3.5 4 5.0 5.5 1.0 1.5 mA mA mA mA mA mA mA mA STLC3080 ELECTRICAL CHARACTERISTICS (continued) Symbol IBAT Parameter VBAT supply current Test Condition H. I. Feeding On-Hook From 0 to 70C From -40 to 85C SBY On-Hook From 0 to 70C From -40 to 85C Active On-Hook From 0 to 70C From -40 to 85C Power Down From 0 to 70C From -40 to 85C Any operating mode Min. Typ. Max. 0.5 1.0 2.5 3.5 4.0 5.0 1.0 1.5 100 Unit mA mA mA mA mA mA mA mA A Fig. IDD VDD Supply Current LOGIC INTERFACE INPUT TIMING t1 t3 t2 t1 t2 t3 t4 t5 t6 Min. 100ns 100ns 250ns Max CSIN D0.1.2,R0.1 100ns 100ns 250ns CSOUT DET, GDK t4 t6 t5 D98TL312 Note: All measurements are performed with 100pF on outputs pin and with TTL compatible voltage levels. Figure 4. Test Circuit. VCC VDD VREL ZAC1 ZAC 12.5K ZA 15K CCOMP 220pF RS 2.5K RX TX ZAC RS RX TX ZB CH 220pF ZB 15K VCC VDD AGND BGND RGND REL0 REL1 RELR PCD RPT1 20 TIP LCP 1511 RPR2 30 LB RT RPT2 30 LA VBRPR1 20 MODE D0 D1 D2 MODE D0 D1 D2 R0 R1 DET GDK/AL CSIN CSOUT RES CKRING TTXIN CAC ILTF RDC RDC 1.5K CRT CRT 470nF IREF RLIM RING STLC3080 RT1 RS1 600K RS2 600K RT2 QEXT BD140 VREG BASE VBAT D1 1N4448 CSVR CREV RTH RTH 26.1K CREV 47nF CSVR 100nF VBRR 600 CONTROL INTERFACE R0 R1 DET GDK/AL CSIN CSOUT RES CKRING TTX VRING VB- RDA 10K RTTX 3.75K CTTX 1F CAC + 10F REF 30.1K RLIM 51.1K D98TL313F 13/23 STLC3080 APPENDIX A The flow-chart in Fig.A1 describes the sequence of state machine supervising the STLC3080 operation when the control is set for Active mode, D0 D1 D2= 1 X X. The state machine is a synchronous sequential circuit internally clocked by a free running oscillator ; the ringing frequency applied at the CKRING input is used to generate the long time delay WTIME=128xCKRING necessary for proper operation as further described. External control is supposed to be set for Active mode : D0 D1 D2= 1 X X. OH-HI : line status flag , set High when Off-Hook condition is detected in High Impedance Feeding; it differs from OHK because it's sensitive to the longitudinal current. OHK: line status flag , set High when Off-Hook condition is detected in Stand-By or in Active mode; it differs from OH-HI for its immunity to longitudinal current . DLY: time-out flag, it is set High to resume, with a given delay, the High Impedance Feeding when an On-Hook condition (OHK=Low) is detected in Stand-By or Active state. 1) Note that in this section the word "mode" has been used to indicate the operating status set with D0, D1 and D2 pin: the word "state" has been used to indicate an internal status of the finite state machine. Flow-chart Description H) A Reset condition, generated at Power On or setting RES pin Low, forces a Power-Down condition. A) High Impedance Feeding is entered after the Active mode word is set and its maintained until an Off-Hook condition is detected (OHHI=High) ; in this case Stand-By state entered. B) Stand-By state is set to perform a validity check of the Off-Hook status of the line before entering Active state. If it is confirmed (OH=High), immediately Active state is entered. If not , Stand-By state remains set for a time period WTIME generated through a counter that times out after 128 x CKRING ; DLY=High signals the state machine the time out to resume the High Impedance Feeding. An OHK = High detected during WTIME will immediately enter Active state. C) Active state is set for conversation and DET=Low signals to the controller the Off-Hook condition of the line. The status remains set as long as OHK=High (Off-Hook). D) When OHK=Low is detected (On Hook), DET is immediately set High whereas Active state is maintained for the period WTIME; when it expires DLY is set High and High Impedance Feeding is resumed. If, during WTIME, OHK=High is detected Off Hook), the state is returned to C) , i.e. Active with DET=Low. E) Ringing mode is set when D0 = D1 = 0 and D2 = 1. After ring trip detection the SLIC is automatically set in Active state (reverse or normal polarity according to D2 value set before ringing mode). Ring trip detection is indicated by DET pin: when it happens the SW must remove the ringing mode word (001) and set the Active mode word (100). F) On-Hook Tx mode is selected when D0 = 0, D1 = 1 and D2 = X. After Off Hook detection the SLIC is automatically set in Active state. 14/23 STLC3080 Figure A1. 15/23 STLC3080 APPENDIX B STLC3080: allowed Rfeed values vs. Ilim The STLC3080 device has been designed in order to fit in a small SMD package (TQFP44). This target has been achieved by using a dedicated circuit for power management based on one external transistor (Qext). The particular power management circuit adopted allows to define the percentage of power dissipated on the SLIC itself and on the Qext. The sharing percentage is defined by the Rfeed value, in particular the higher is Rfeed, the higher is the percentage dissipated on the SLIC. Rfeed represents the DC feeding impedance at TIP/RING terminals (including 2xRp) when the SLIC is in the resistive feed region of the DC characteristics. Since the max. power dissipation inside the SLIC is limited it is important to know which value of Rfeed can be implemented without exceeding the max power allowed in the SLIC. In order to define the allowed Rfeed values several other parameters should be considered, in particular: Pdslic: Max allowed power dissipation on SLIC, two values are considered: 1.1W for 70C Tamb application; 0.9W for 85C Tamb application; Pdqext: Max allowed power dissipation on Qext, three values are considered: 1.0W 1.5W 2.0W These values depend on the package and the assembly of the Qext. Ilim: Programmed constant current value, continuous variations are considered from 20mA to 50mA. Vbat: Battery voltage, three values are considered: 48V 54V 62V The following diagrams show the allowed Rfeed values depending on the above parameters. three diagrams are shown each one for a particular battery (Vbat = -48V, -54V, -60V). In each diagrams you can find an upper and a lower limits for the Rfeed value: The upper limit is defined by one of the two b1, b2 curves. b1 is the limit when max. power on SLIC is equal to 0.9W (Tamb = 85C) b2 is the limit when max. power on SLIC is equal to 1.1W (Tamb = 70C) The lower limit is defined by one of the three a1, a2, a3 curves. a1 is the limit when max. power allowed on Qext is equal to 1.0W a2 is the limit when max. power allowed on Qext is equal to 1.5W a3 is the limit when max. power allowed on Qext is equal to 2.0W Figure B1. Rfeed allowed values vs. Ilim (Vbat = -48V). 16/23 STLC3080 Figure B2. Rfeed allowed values vs. Ilim (Vbat = -54V). Figure B3. Rfeed allowed values vs. Ilim (Vbat = -60V). EXAMPLE: Considering the following parameters: Vbat = -48V, max Tamb = 70C, Ilim = 25mA, Qext able to dissipate 1W, the possible values of Rfeed can be found in fig. 1 and are limited by the b2 curve (upper limit) and the a1 curve (lower limit). In particular considering the Ilim = 25mA the Rfeed allowed range will be: 500 < Rfeed < 1700 17/23 STLC3080 APPENDIX C STLC3080 Test Circuits referring to the application diagram shown in figure 4 and using as external components the typ. values specified in the Figure C1. Receive Gain. "External Components", find below the proper configuration for each measurement. Figure C2. THL Trans Hybrid Loss. Rp TIP 300 VL 300 TX Vtx TIP 300 Vl 300 RING TX STLC 3080 test circuit STLC 3080 test circuit RX Vrx Rp RING RX Vrx G42 = 20log (Vl / Vrx ) THL = 20log (Vrx /Vtx ) Figure C3. T/L Transversal to Longitudinal Conversion Figure C4. Transmit Gain. Rp TIP 300 Vl Vtl 300 RING RX Vrx TX 600 TIP TX STLC 3080 test circuit STLC 3080 E Vtx test circuit RING RX T/L = 20log (Vl / Vtl ) G24 = 20log (2Vtx / E ) Figure C5. L/T Longitudinal to transversal Conversion. Figure C6. 2W Return Loss. 600 300 TIP TX TIP TX 10uF STLC 3080 1000 STLC 3080 test circuit Vac E 300 test circuit E 1000 Vs RING RX RING RX L/T = 20log ( E / Vac ) 2WRL = 20log ( E / 2Vs ) 18/23 STLC3080 Figure C7. Idle channel psophometric noise at TX port. Figure C8. Idle channel psophometric noise at line terminals. TIP TX TIP TX STL C 3080 600 Vtx 600 STLC 3080 Vtx test circuit Vl test circuit RING RX RING RX V4wp = 20log (Vtx / 0.775V ) V2wp = 20log (Vl / 0.775V ) Figure C9. PSRRC = Power Supply Rejection VCC to 2W Port PSRRB = Power Supply Rejection VBAT to 2W Port TIP TX 600 Vl STLC 3080 test circuit RING Vbat/Vcc RX PSRRB = 20log (VnVbat / Vl ) PSRRC = 20log (VnVcc / Vl ) Vn = 0.1Vrms 19/23 STLC3080 APPENDIX D RINGING MODE AND RING TRIP DETECTION In ringing mode the STLC3080 provides: - Relay driver capability (relay is synchronized with low level of CKRING) - Ring-Trip detection The monitor of the line state is performed by sensing the line current converted into a voltage drop across the RR resistor connected in series to the line. This voltage is read via RS1and RST2 input pins of a differential stage that identifies, during the ringing phase, the ON/OFF HOOK state of the line (see Fig. D1). The Ring-Trip condition is detected by sensing the DC component of the line current, rejecting the AC component. With RR = 600 the RingTrip threshold is: Iline>7.5mA When the Ring-Trip is detected, the STLC3080: - deactivates the ringing relay RELR (if CKRING is low); - indicates the ring-trip detection by setting DET=low; - forces the Active state. The information at RELR and DET pins is lached and it doesn't change opening the current loop. To reset the latched informations the Active or On-Hook Transmission mode have to be entered (in general changing the device mode the latched information is removed). Although the ring-trip detection sets DET to signal the line status, there is a substantial difference respect to the on/off-hook detection. In Ringing mode on-hook condition, an AC current is present on the line. The ring-trip detector rejects the AC Figure D1.ring trip circuit block diagram. VCC component by integrating the line current: the detection threshold can be reached only if the line current has a DC component higher than the threshold. As a consequence the response is not immediate (as it is for off-hook in Active state): it takes an amount of time that is dependent on the DC current value (i.e. on the line length). The AC rejection and the delay depend on the CRT capacitor value (see Fig.D1). When the voltage on the capacitor exceeds 3V, the Ring-Trip is detected (see fig.D3). CRT should be selected in order to avoid that during one half sinewave cycle, in on-hook, its voltage VCRT exceeds 3V (ring-trip threshold). The minimum value of CRT can be carried out with the following formula: Ccrt > 6F/Fring With Fring = 20Hz, you obtain a Ccrt = 390nF. When the CRT capacitor is selected, it must be considered that it is also used for the rejection of the common mode current. In this case the minimum value of the CRT capacitor can be carried out with the following formula: Ccrt > (Ip/Fl) 560F Where Ip is the peak of the longitutudinal current and Fl is the frequency of this current. With Ip = 25mA @ Fl = 50Hz you obtain 330nF. For this reasons the suggested value for typical central office application is 470nF. ILINE RS1 RR RS2 IRING ICRT CRT COMP 3Volt DET Ith=7.5uA(typ) VB IRING=ILINERS1/RR RS1=RS2 20/23 STLC3080 Figure D2. relation between Icrt and Iline. ICRT +30uA ILINEth=7.5mA(typ) ILINEth=IthRS1/RR ILINE (if RR=600 and RS1=RS2=600K) -30uA RS1 must be connected to the positive RR; RR should be connected directly to the ringing generator as it is in the figure. The ratio between RS1 and RR must be chosen considering that there is an offset current in the input stage equal to 7.5A. This offset has been introduced to take in account the leackage current of the line. In fig.D2 is shown the relation between the CRT charging current I CRT and the line current ILINE. In the range -30A Vring=60Vrms @ f=25Hz VB=-48Volt DET RING wire CRT OFF_HOOK RING-TRIP DETECTION 21/23 STLC3080 DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 1.40 0.37 mm TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030 0.055 0.014 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008 OUTLINE AND MECHANICAL DATA TQFP44 (10 x 10) 0(min.), 3.5(typ.), 7(max.) D D1 A1 33 34 23 22 0.10mm .004 Seating Plane A A2 E1 B 44 1 11 12 E B e C L K TQFP4410 22/23 STLC3080 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 23/23 |
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